We Are:

The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.

You Are:

An experienced SoC Integration Engineer

The Work:

The ideal candidate can help along the design flow to establish synthesis runs with the related timing constraints, perform Lint, CDC, DFT checks, support regression and release process and analyze STA timing results.

Here’s what you need:

• A minimum of 3 years of experience with STA (Static Timing Analysis) and PrimeTime and related timing constraints methodology and SDC constraints language

• A minimum of 3 years of experience RTL Integration, 3 rd Party IP RTL through Lint, CDC check, DFT check with spyglass or VC static and generate clean reports

• Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

• Background in subsystem integration

• There is a need to have proper representation for NEEV

• There is some customization so having RTL background would be good

• Basic Python knowledge with good understanding of digital design

• Background in AMBA Protocol such as, AXI, APB, AHB, QCH,

• Expected to deliver basic design collateral : Lint, CDC, RDC, UPF

• Basic understanding of CoreConsultant

• Half the team exposed to UVM and basic to good UVM working/debug background knowledge

Bonus points if:

• Proficient with System Verilog/Verilog RTL source code

• Proficient with Synopsys Design Compiler and/or Design Compiler Ultra

• Python, tcl and other typical scripting languages

• Debug flow and tool errors

• Familiar with vaml

• Familiar with setting up and debugging GLS runs

• Familiar with bug tracking systems like Jira

• Familiar with revision control systems like Git

Nice to have:

• Low power design background for front-end

• Background in high speed IOs and Protocol such as MIPI, PCIE, DDR, Serdes

• Basic understanding of MMU-600, SST, VFC and SEQ [custom DMA]

ManpowerGroup is committed to providing equal employment opportunities in a professional, high quality work environment. It is the policy of ManpowerGroup and all of its subsidiaries to recruit, train, promote, transfer, pay and take all employment actions without regard to an employee's race, color, national origin, ancestry, sex, sexual orientation, gender identity, genetic information, religion, age, disability, protected veteran status, or any other basis protected by applicable law.