Floorplanning of the chip or block - IO pad ring design; Macro placement; and Power grid design. Place and route - Physical synthesis, placement legalization, with ideal clock timing and constraints fix; Clock tree synthesis - clock balancing, analyzing timing, and fixing timing; Routing with DRC cleanup; Signal integrity analysis; Timing closure based on signoff tools; IR drop analysis with qualified input; Formal verification; and Low power verification checks. Physical verification - DRC cleanup of base and metal; Layout versus schematic clean-up; and Chip finishing for manufacturability. Telecommuting permitted. Position requires a Bachelor’s or a foreign equivalent in Electronics and Communications Engineering, Computer Engineering, Computer Science, Electrical Engineering, or Engineering diploma with concentration on VLSI, and 5 years of work experience in any occupation in which the required experience was gained.To apply, email resume to Alice Choi at Alice.Choi@mobileye.com & ref job #7399991

Minimum Salary: 170000 Maximum Salary: 200000 Salary Unit: Yearly